How often does the "slow path" actually trigger? With 32 TLB entries covering 128 KB, Intel claimed a 98% hit rate for typical workloads of the era. That sounds impressive, but a 2% miss rate means a page walk every 50 memory accesses -- still quite frequent. So the 386 overlaps page walks with normal instruction execution wherever possible. A dedicated hardware state machine performs each walk:
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arr[j + gap] = key;
"I think the pressure of the 'lights, camera, action' was making me a bit flustered," she laughs, "because if you'd asked those questions to me in a room like this, I would have known them instantly.